ASIC Design for Test Hardware Engineer

  • Location:
    San Jose, California, US
  • Area of Interest
    Engineer - Hardware
  • Job Type
    Professional
  • Technology Interest
    *None
  • Job Id
    1211449
New

What You'll Do

 As a member of Cisco’s Central DFT team, you’ll be responsible for architecting, implementing and verifying the ASIC Design-for-Test (DFT) features that support silicon screening, in-system test, debug and diagnostics.  You will drive DFT post-silicon feature validation and be a key interface to our ATE Test team.  You’ll be responsible for the development of innovative DFT IP in collaboration with the Central Hardware Group to functionally test ASICs in the system that have a focus on debug-capability and fault isolation, including  functional traffic test IP development.  You’ll work closely with the ASIC design teams to enable the integration and validation of the Test logic in all phases of the design and back-end implementation flow.   You will interface with our ASIC vendors and drive Cisco’s DFT requirements. You will be responsible for inventive DFT for new silicon device models, including silicon photonic chipsets, bare die, stacked die and 2.5D and 3D and driving re-usable test and debug strategies.   This is a hands-on technical lead position spanning the entire product life cycle.

Who You'll Work With

You will collaborate with ASIC design teams in the Central Hardware Group, board/system hardware engineers in various business units, peer groups of packaging, ATE testing, component engineering and New Product introduction engineers.  You’ll work with our third-party ASIC vendors who manufacture our silicon.  As a member of this team you will be involved in creating cutting edge next generation networking chips and driving DFT quality throughout the entire Implementation flow. 

Who You Are

You are an ASIC Design for Test(DFT) engineer with  7+ years of experience including:

Excellent knowledge of latest state-of-the-art trends in DFT and test.

Hands-on design and verification experience with JTAG protocols, Scan and BIST architectures, including Logic BIST, memory BIST, IO BIST

Verification skills include, System Verilog, UVM, Logic Equivalency checking and validating the test-timing of the design.

Experience working with Gate level simulation and debug with VCS and other simulators.

Experience with DFT silicon sign-off for tape out.

Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 

Strong verbal communication skills and ability to thrive in a dynamic environment.

Great RTL design, verification, debug and scripting skills with minimal oversight.

Scripting skills: Python/Perl.

Bachelor's or a Master’s Degree in Electrical or Computer Engineering required

 

Why Cisco
We connect everything: people, processes, data, and things. We innovate everywhere, taking bold risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals. And we do it in style with unique personalities who aren’t afraid to change the way the world works, lives, plays and learns. 

We are thought leaders, tech geeks, pop culture aficionados, and we even have a few purple haired rock stars. We celebrate the creativity and diversity that fuels our innovation. We are dreamers and we are doers. 

We Are Cisco.

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