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ASIC Design Verification Engineer (Markham, ONT)

Qualcomm Inc.


Location:
Markham
Date:
04/20/2018
2018-04-202018-05-19
Job Code:
1963554
Qualcomm Inc.
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Job Details

Job Title ASIC Design Verification Engineer (Markham, ONT)
Jobid 1963554
Location: Markham, CAN
Job Description:
**Job Id**
E1963554
Job Title
ASIC Design Verification Engineer (Markham, ONT)
Post Date
04/16/2018
Company
-
Division
Qualcomm Technologies, Inc.
-
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area
Engineering - Hardware
Location
Canada - Markham
Job Overview
Work with design and verification engineers to verify a variety of digital ASIC designs. Work involves definition and execution of detailed block test plans. Define and implement test environment architectures, coverage models and assertions. Verify design performance requirements. Debug RTL, gate level and power aware simulations. Automation of work flows to improve productivity. Use of simulation tools, coverage tools and formal evaluation engines. Use of directed and constrained random verification strategies. Use of languages such as HDL, C, PERL. Use of System Verilog assertions, UVM and function coverage models.


The responsibilities of this role include:


Working under close supervision.


Taking responsibility for own work and making decisions with limited impact; Impact of decisions is readily apparent; errors made typically only impact timeline (i.e., require additional time to correct).


Using verbal and written communication skills to convey basic, routine factual information about day-to-day activities to others who are fully knowledgeable in the subject area.


Completing most tasks with multiple steps which can be performed in various orders; some planning and prioritization must occur to complete the tasks effectively; mistakes may result in some rework.


Exercising some creativity to troubleshoot technical problems or deal with novel circumstances.


Using deductive problem solving to solve moderately complex problems; most problems have defined processes of diagnosis/detection; some limited data analysis may be required.


PRINCIPAL DUTIES AND RESPONSIBILITIES:


Uses tools/applications (i.e., RTL simulators, formal evaluation engines etc.) to execute the test plan for a specific part of a block according to design requirements provided.


Resolves verification problems by applying sound ASIC engineering practices with some supervision.


Executes the verification strategies of ASICs, SoC, and IP cores of own specific assigned part of a block or IC Package with supervision from project lead.


Writes basic tests and regressions to identify any bugs in own work.


Interprets the results of performance checks and reports them to team lead.


Supports the innovation of ASICs, SoC, IP cores, verification methodologies.


Writes, reviews, and edits technical document in accordance with template requirements.


Communicates directly with lead on any significant deviations from the Plan of Record for specific assigned part of a block in a timely manner.


Participates in design or verification reviews and project meetings.


Provides input to team lead regarding areas for process and procedural improvement.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field.
Preferred Qualifications
Bachelor's degree in Electrical Engineering, Computer Science, or Computer Engineering.


6+ months experience with ASIC/FPGA design verification.


6+ months experience with scripting tools and programming languages.


6+ months experience with design verification methods.
Education Requirements
Bachelor's degree in Science, Engineering, or related field.
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.


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