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Design Verification CAD Manager

Qualcomm Inc.


Location:
Bangalore
Date:
05/18/2018
2018-05-182018-06-16
Job Code:
1963631
Qualcomm Inc.
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Job Details

Job Title Design Verification CAD Manager
Jobid 1963631
Location: Bangalore, IND
Job Description:
**Job Id**
T1963631
Job Title
Design Verification CAD Manager
Company
-
Division
Qualcomm Technologies, Inc.
-
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area
Engineering - Hardware
Location
India - Bangalore
Overview
Job Overview:
Verification Design Automation Mgr. will responsible for managing the BDC front-end CAD team. Collaborating with key stakeholders from Design & DV teams along with WW CAD leads. Developing, implementing, and deploying automated methodologies and tool flows that are used to validate a multitude of wireless chips and IP cores/blocks. As part of the Verification CAD, this position plays a critical role in driving next-generation verification methodologies through the deployment of semi and full-custom EDA tools that are used widely across the globe by the various ASIC digital design/verification teams.
As a Mamager of the EDA CAD verification design automation team you will: Hire, Train and build the teams to develop and contribute technical aspects of many advanced verification methodologies and initiatives.
+ Key areas of focus involve Gate level Simulations, Low power simulation, Emulation, Simulation acceleration, and UVM methodology.

+ Work closely with cross-functional teams by leveraging domain-specific expertise and sharing/coordinating prototyping efforts, testing, and support.

+ Responsible for developing, implementing, and deploying advanced verification methodologies and flow automations across all chips and IP cores/blocks, as well as across simulation acceleration, Emulation, and post silicon validation. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.Minimum Qualifications:

+ 15 years of experience in ASIC/SoC Design Verification CAD including

+ Experience in scripting for automation of design methodologies & flows.

+ Experience using latest Verification methodologies such as System Verilog, and UVM

+ Working knowledge in one or more of the following: C, C++, Python, TCL or Perl.

+ Good to have hands-on experience in Low power Verification using VCS in UPF2.0. Experience with Multi-voltageMulti-mode designs will be plus

+ Experience evaluating, designing, and deploying EDA tools in the area of Functional Verification, Simulation acceleration and Emulation.

+ Positive attitude and sound aptitude, willing to perform under challenging environment and ready to show ownership
Education Requirements
Required: Bachelor's, Electrical Engineering
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.


Apply on the Company Site
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