ENGINEER.III.HARDWARE ENGINEERING.CISCO

  • Location:
    Bangalore, Karnataka, India
  • Area of Interest
    Engineer - Hardware
  • Job Type
    Professional
  • Technology Interest
    *None
  • Job Id
    1028495

What You'll Do

Verifying complex ASIC/FPGAs at the heart of Cisco's networking products requires a unique combination of talents and a drive for perfection in the face of ever growing complexity.

 

Who You'll Work With

To accomplish this task, the design verification team requires software engineering acumen, cutting edge languages and EDA tools, deep understanding of the ASIC/FPGA design, and broad understanding of the system context.

Who You Are

Responsibilities within team:

* Test bench design and implementation.
* Test & coverage plan definition.
* Constrained random test development.
* Coverage specification & analysis.
* Reference model design and implementation.
* Automation of the regression test suite
* Collaboration with architects, logic design, and software engineers.
* Architecture review.
* Micro-architecture and code reviews.
* Contribution to the methodology adoption in the team.
* Lab debug simulation support


The candidate has to work as a Senior verification engineer for high end data path as well as control FPGAs as a part of Centralized Hardware Group in Cisco. He/she is also expected to contribute throughout all stages of the FPGA development process, such as:

* Collaboration with architects, logic design, and software engineers.
* Architecture review.
* Micro-architecture and code reviews.
* Contribution to the methodology adoption in the team.
* Lab debug simulation support

Why Cisco

* Proficiency in OOPs, Verilog & System Verilog.
* Solid verification skills : planning, problem solving, debug, adversarial testing and random testing.
* Project based work experience with UVM/VMM methodologies.
* Candidate must have experience with architecting the testplan & test bench.


* Hands on experience with Ethernet based protocols, PCIe, AXI, memory controllers, OTN etc. will be an added advantage. 
* Familiarity with VCS simulation flow, knowledge of coverage & assertions is desirable.

Relevant Experience :
5 to 8 years of experience in functional verification.


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