Hardware Engineering - Technical Leader

  • Location:
    San Jose, California, US
  • Area of Interest
    Engineer - Software
  • Job Type
  • Technology Interest
    Internet of Everything
  • Job Id
What You'll Do:

You will be part of a team that is responsible for every phase of the ASIC development process from architecture definition, implementation, verification, physical design, lab bring-up and release to volume production.  You will be exposed to state-of-the-art design, verification and physical design methodologies created by one of the most advanced ASIC teams in the world.  

Who You'll Work With:

Cisco’s CAG (Central ASIC Group) develops custom silicon for products that generate $20+ Billion in revenue for the company.  You will work with Systems and SW engineers to innovate in major application areas and will have immense learning opportunities bringing new technologies and solutions to market.  Our team is extremely diverse and experienced.  We have the resources, money and knowledge to continue to excel in a world where many companies can no longer afford to develop their own custom silicon.   Our ASICs and scale provide the differentiation that will allow Cisco to dominate the digital transition that is now well under way.

Who You Are:

Contribute to the architecture, micro-architecture and design of complex, high-performance, and highly integrated ASICs used in Cisco's networking products.

  • Lead and contribute to architecture, micro-architecture, and RTL specifications and development.
  • Lead and participate in design environment and methodology.
  • Carry out RTL capture and clean delivery of design.  
  • Take the design through physical design and implementation for an optimal power, area, and complexity
  • Engage in post-silicon bring-up and debug in the lab.
  • Mentor and enable other engineers.
  • Lead and oversee design, working with geographically diversified team of engineers.

Skills Required:
  • Experience in high-performance ASIC design.
  • Good understanding of ASIC design and verification methodologies and flows.
  • Hands-on experience with HVL and HDL languages and tools, scripting and programming languages (verilog, SV, C++, Perl, etc.).  
  • Understanding and working knowledge to deal with Synthesis, Lint, formal verification tools from Synopsys / Cadence / Mentor Graphics / other CAD vendors
  • Good problem solving skills.
  • Good communication skills and a team player.
  • Networking knowledge preferred, but not essential.

  • Complex ASIC architecture and design experience  
  • Must have delivered a few ASIC designs from concept to shipment.
  • Good communication and teamwork skills.

Why Cisco?

We connect everything: people, processes, data, and things. We innovate everywhere, taking bold risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals. And we do it in style with unique personalities who aren’t afraid to change the way the world works, lives, plays and learns.

We are thought leaders, tech geeks, pop culture aficionados, and we even have a few purple haired rock stars. We celebrate the creativity and diversity that fuels our innovation. We are dreamers and we are doers.

We Are Cisco.

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