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Physical Design Lead - QCT, Cork, Ireland (M)

Qualcomm Inc.


Location:
Cork
Date:
05/24/2018
2018-05-242018-06-22
Job Code:
1962894
Qualcomm Inc.
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Job Details

Job Title Physical Design Lead - QCT, Cork, Ireland (M)
Jobid 1962894
Location: Cork, IRL
Job Description:
**Job Id**
E1962894
Job Title
Physical Design Lead - QCT, Cork, Ireland (M)
Post Date
04/24/2018
Company
-
Division
Qualcomm Technologies, Inc.
-
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area
Engineering - Hardware
Location
Ireland - Cork
Job Overview
PTEV Team - Product and Technology Enablement Vehicles is part of DTECH PPA RD team working on latest advanced technology nodes across foundries. Job responsibility includes:- Independent planning and execution of Netlist-to-GDSII. Full exposure to all aspects of design flows like floorplanning, placement, CTS, routing, crosstalk avoidance, physical verification Well versed with the block level timing closure (STA), timing closure methodologies, ECO generation and predictable convergence. Well versed with parasitic extraction, LVS/DRC and other Physical verification checks. Should be able to provide clear directions to the team wrt PNR issues Drive methodology with help of internal and external CAD/EDA teams for faster design convergence. Well aware of place and route methodologies and hands on experience with timing convergence. Work closely with the foundry teams to enable Physical design on the cutting edge technology nodes. Work closely with EDA vendors to ensure tool readiness for supporting new DRC and design requirements. Candidate would also work on integrating / deploying these PD technologies and methodologies in product chips by working with CAD team, enablement team, DTECH team, product SoC team
Minimum Qualifications
+ 5+ years of experience in Physical Design

+ Should have good exposure physical design methodology

+ Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 5+ years of experience in IC design Experience in leading block level or chip level Timing closure & Physical Design activities.

+ Work independently in the areas of RTL to GDSII implementation Ability to collaborate and resolve issues with regard to constraints validation, verification, STA, Physical design, etc.

+ Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)

+ Tcl/Perl/Python scripting Willing to handle technical deliveries with a small team of engineers.

+ Strong problem-solving skills
Preferred Qualifications
+ ASIC Design knowledge and in-depth experience in physical design

+ Understanding of deep sub-micron design problems including PNR challenges on FinFET technology

+ Delivery of blocks in cutting edge technology nodes from DFT netlist to GDS
Education Requirements
Required: Bachelor's, Computer Engineering and/or Electrical Engineering

Preferred: Master's, Computer Engineering and/or Electrical Engineering
WE INVENT THE TECH THE WORLD LOVES, SO IF YOU ARE INTERESTED IN LEARNING MORE https://www.qualcomm.com/weinvent
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.


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