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Physical Design Methodology & (CAD/EDA) Careers in Bangalore

Qualcomm Inc.


Location:
Bangalore
Date:
04/20/2018
2018-04-202018-05-19
Job Code:
1962094
Qualcomm Inc.
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Job Details

Job Title Physical Design Methodology & (CAD/EDA) Careers in Bangalore
Jobid 1962094
Location: Bangalore, IND
Job Description:
**Job Id**
T1962094
Job Title
Physical Design Methodology & (CAD/EDA) Careers in Bangalore
Company
-
Division
Qualcomm Technologies, Inc.
-
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area
Engineering - Hardware
Location
India - Bangalore
Overview
As a member of QCT EDA team, the candidate will help develop and support the SOC design flow in advanced technologies and will be working closely with design teams developing state-of-the-art SOCs and High performance cores in 10nm and smaller technologies. This position requires in-depth understanding of the IC implementation flow from RTL to GDS2 and the challenges posed by advanced technologies in areas of Performance- Power trade-off, DFM, Advanced timing analysis and system level power integrity. The successful candidate will show detailed understanding of physical synthesis, design partitioning, floor planning, place and route, timing and power analysis required for establishing flows and methodology for physical design flow in 10nm and smaller technologies
+ Work with design team and technology teams to rollout robust physical design flows, identify areas for flow improvement, develop plans and implement improvements.

+ Support ASIC physical design tools from Synopsys, Mentor and Cadence.

+ Develop flows for high performance cores with optimal power, area and DFM quality.

+ Provide tool support and issue debugging services to design teams.

+ Develop and maintain 3rd party tool integration and productivity enhancement routines

+ 2-15 years of experience within the PD environment is required.

+ Superior TCL, Perl programming skills.

+ Knowledge on PNR tools (Icc/Innovus/Olympus/First Encounter) , Primetime, redhawk, is required.

+ Knowledge of Physical Design methodologies is desired: Floorplanning, Timing closure methodology, Power reduction, Area reduction, clock tree optimization.

+ Ability and drive to understand the motivation for tools, where they fit into the flow, how to prioritize features and to decide the best way to implement

+ Ability to ramp-up in new areas and excellent communication skills desired.
Education Requirements
Required: Bachelor's, Computer Engineering, Computer Science and/or Electrical Engineering.

Preferred: Master's, Computer Engineering, Computer Science and/or Electrical Engineering.
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.


Apply on the Company Site
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