Senior Design Verification Engineer

  • Location:
    San Jose, California, US
  • Area of Interest
    Engineer - Hardware
  • Job Type
  • Technology Interest
    Internet of Everything
  • Job Id
What You'll Do:

You will be part of a team that is responsible for every phase of the ASIC development process from architecture definition, implementation, verification, physical design, lab bring-up and release to volume production.  You will be exposed to state-of-the-art design, verification and physical design methodologies created by one of the most advanced ASIC teams in the world.  

Who You'll Work With:

Cisco’s CAG (Central ASIC Group) develops custom silicon for products that generate $20+ Billion in revenue for the company.  You will work with Systems and SW engineers to innovate in major application areas and will have immense learning opportunities bringing new technologies and solutions to market.  Our team is extremely diverse and experienced.  We have the resources, money and knowledge to continue to excel in a world where many companies can no longer afford to develop their own custom silicon.   Our ASICs and scale provide the differentiation that will allow Cisco to dominate the digital transition that is now well under way.

Who You Are:

Participate in the architecture and verification of complex, high-performance, and highly integrated ASICs used in Cisco's networking products.

  • Participate in architecture definition and modeling.
  • Contribute in micro-architecture specification and reviews.
  • Partake in verification environment architecture and methodology.
  • Carry out testplanning and execution of testplan.
  • Cooperate with design team members to effectively test, verify, and debug DUT for successful tapeout.
  • Engage in post-silicon bringup and debug in the lab.
  • Mentor and enable other engineers.
  • Lead and oversee design verification efforts of a cluster of blocks.
Skills Required:
  • Experience in high-performance ASIC verification.
  • Good understanding of ASIC design and verification methodologies and flows.
  • Hands-on experience with HVL and HDL languages and tools, scripting and programming languages (verilog, SV, C++, Perl, etc.).
  • Proficient in object oriented programming.
  • Good understanding of random stimulus generation methodology.
  • UVM knowledge a plus.
  • Good problem solving skills.
  • Good communication skills and a team player.
  • Networking knowledge preferred, but not essential.
  • Complex ASIC verification experience.
  • Proficient in object oriented programming.
  • Good understanding of random stimulus generation methodology.
  • Good communication and teamwork skills.

Why Cisco?

We connect everything: people, processes, data, and things. We innovate everywhere, taking bold risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals. And we do it in style with unique personalities who aren’t afraid to change the way the world works, lives, plays and learns.

We are thought leaders, tech geeks, pop culture aficionados, and we even have a few purple haired rock stars. We celebrate the creativity and diversity that fuels our innovation. We are dreamers and we are doers.

We Are Cisco.

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