Senior DV Engineer

  • Location:
    San Jose, California, US
  • Area of Interest
    Engineer - Software
  • Job Type
  • Technology Interest
    Internet of Everything, Networking
  • Job Id
What You'll Do:

You will be part of a team that is responsible for every phase of the ASIC development process from architecture definition, implementation, verification, physical design, lab bring-up and release to volume production.  You will be exposed to state-of-the-art design, verification and physical design methodologies created by one of the most advanced ASIC teams in the world.  

Who You'll Work With:

Cisco’s CAG (Central ASIC Group) develops custom silicon for products that generate $20+ Billion in revenue for the company.  You will work with Systems and SW engineers to innovate in major application areas and will have immense learning opportunities bringing new technologies and solutions to market.  Our team is extremely diverse and experienced.  We have the resources, money and knowledge to continue to excel in a world where many companies can no longer afford to develop their own custom silicon.   Our ASICs and scale provide the differentiation that will allow Cisco to dominate the digital transition that is now well under way.

Who You Are:

The candidate will execute tasks related to building the verification test environment for chip and sub-system DV – including test plan development and execution.

Desired Skills and Tasks
  • Must be productive in setting technical priorities, self-starting, and have strong communication skills.
  • Work experience in SoC verification using System Verilog, C/C++, or UVM: 6+ years with MSEE or 8+ years with BSEE.
  • Expertise in developing block level and system level verification environments.
  • Expertise to develop BFMs, checkers, monitors, and scoreboards.
  • Experienced with Synopsys, Cadence and Mentor design and verification products
  • Must have capability to debug test failures to find the root cause both at RTL and gate level.
  • Expertise in L2/L3 forwarding, Ethernet (802.3), Switching and Routing domain knowledge.
  • PLL, serdes and/or PHY experience; ARM, memory subsystem experience and Emulation (Veloce, Palladium) is a plus.

Why Cisco?

We connect everything: people, processes, data, and things. We innovate everywhere, taking bold risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals. And we do it in style with unique personalities who aren’t afraid to change the way the world works, lives, plays and learns.

We are thought leaders, tech geeks, pop culture aficionados, and we even have a few purple haired rock stars. We celebrate the creativity and diversity that fuels our innovation. We are dreamers and we are doers.

We Are Cisco.



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