TECHNICAL LEADER ENGINEERING

  • Location:
    San Jose, California, US
  • Area of Interest
    Engineer - Software
  • Job Type
    Professional
  • Technology Interest
    Internet of Everything, Networking
  • Job Id
    1208962
New

Job Description

The candidate will execute tasks related to building the verification test environment for chip and sub-system DV – including test plan development and execution.

Desired Skills and Tasks
Must be productive in setting technical priorities, self-starting, and have strong communication skills.

  • Work experience in SoC verification using System Verilog, C/C++, or UVM: 6+ years with MSEE or 8+ years with BSEE.

  • Expertise in developing block level and system level verification environments.

  • Expertise to develop BFMs, checkers, monitors, and scoreboards.

  • Experienced with Synopsys, Cadence and Mentor design and verification products

  • Must have capability to debug test failures to find the root cause both at RTL and gate level.

  • Expertise in L2/L3 forwarding, Ethernet (802.3), Switching and Routing domain knowledge.

  • PLL, serdes and/or PHY experience; ARM, memory subsystem experience and Emulation (Veloce, Palladium) is a plus.

 

 


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