Technical Leader

  • Location:
    San Jose, California, US
  • Area of Interest
    Engineer - Software
  • Job Type
  • Technology Interest
    Internet of Everything
  • Job Id


Contribute to the architecture, micro-architecture and design of complex, high-performance, and highly integrated ASICs used in Cisco's networking products.


* Lead and contribute to architecture, micro-architecture, and RTL specifications and development.
* Lead and participate in design environment and methodology.
* Carry out RTL capture and clean delivery of design.

* Take the design through physical design and implementation for an optimal power, area, and complexity
* Engage in post-silicon bring-up and debug in the lab.
* Mentor and enable other engineers.
* Lead and oversee design, working with geographically diversified team of engineers.

Skills Required:

* Experience in high-performance ASIC design.
* Good understanding of ASIC design and verification methodologies and flows.
* Hands-on experience with HVL and HDL languages and tools, scripting and programming languages (verilog, SV, C++, Perl, etc.).

* Understanding and working knowledge to deal with Synthesis, Lint, formal verification tools from Synopsys / Cadence / Mentor Graphics / other CAD vendors
* Good problem solving skills.
* Good communication skills and a team player.
* Networking knowledge preferred, but not essential.


* Complex ASIC architecture and design experience

* Must have delivered a few ASIC designs from concept to shipment.
* Good communication and teamwork skills.

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